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Integrated Circuit Systems, Inc.
ICS93725
DDR and SDRAM Zero Delay Buffer
Recommended Application: DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/ 650 & 735/740/746 style chipsets. Product Description/Features: * Low skew, Zero Delay Buffer * 1 to 13 SDRAM PC133 clock distribution * 1 to 6 pairs of DDR clock distribution * I2C for functional and output control * Separate feedback path for both memory mode to adjust synchronization. * Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs * Frequency support for up to 200MHz * Individual I2C clock stop for power mananagement * CMOS level control signal input Switching Characteristics: * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time for DDR outputs: 550ps 1150ps * DUTY CYCLE: 47% - 53%
Pin Configuration
VDD3.3 SDRAM0 SDRAM1 SDRAM2 SDRAM3 GND VDD3.3 SDRAM4 SDRAM5 BUFFER_IN SDRAM6 SDRAM7 GND VDD3.3 SDRAM8 SDRAM9 SDRAM10 SDRAM11 GND VDD3.3 SDRAM12 SDFB_OUT SDFB_IN GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL_DDR* DDRFB_IN DDRFB_OUT VDD2.5 DDRT5 DDRC5 DDRT4 DDRC4 GND VDD2.5 DDRT3 DDRC3 DDRT2 DDRC2 GND VDD2.5 DDRT1 DDRC1 DDRT0 DDRC0 GND VDD2.5 SCLK SDATA
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
SDRAMFB_OUT PLL1 DDRFB_OUT SDRAM (12:0) Control SEL_DDR* SDATA SCLK Config. Reg. Logic
3 3
Functionality
MODE PIN 48 SEL_DDR=1 SEL_DDR=0 VDD 3.3_2.5 2.5V 3.3V
BUFFER_IN SDRAMFB_IN DDRFB_IN
DDR Mode DDR/SD Mode
DDRT (5:0) DDRCC (5:0)
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ICS93725
ICS93725
Pin Descriptions
PIN NUMBER 1, 7, 14, 20 6, 13, 19, 24, 34, 28, 40 44, 42, 38, 36, 32, 30 43, 41, 37, 35, 31, 29 PIN NAME VDD3.3 GND DDRT (5:0) DDRC (5:0) TYPE PWR PWR OUT OUT OUT PWR IN OUT IN I/O IN OUT IN IN DESCRIPTION 3.3V voltage supply for SDRAM. Ground "Tr ue" Clock of differential pair outputs. "Complementor y" clocks of differential pair outputs. SDRAM clock outputs 2.5V voltage supply for DDR. Single ended buffer input Feedback output for SDRAM Feedback input for SDRAM Data pin for I2C circuitr y 5V tolerant Clock input of I2C input, 5V tolerant input Feedback output for DDR Feedback input for DDR Select input for DDR mode or DDR/SD mode 0=SD mode 1=DDR mode
21, 18, 17, 16, 15, 12, 11, 9, 8, 5, SDRAM (12:0) 4, 3, 2 27, 39, 45 10 22 23 25 26 46 47 48 VDD2.5 BUFFER_IN SDRAMFB_OUT SDFB_IN SDATA SCLK DDRFB_OUT DDRFB_IN SEL_DDR
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ICS93725
Byte 6: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 48 44, 43 42, 41 38, 37 36, 35 32, 31 PWD 1 1 1 1 1 1 1 DESCRIPTION SEL_DDR (Read back only) (Reserved) (Reserved) DDRT5, DDRC5 DDRT4, DDRC4 DDRT3, DDRC3 DDRT2, DDRC2 DDRT1, DDRC1
Byte 7: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 30, 29 21 17, 18 15, 16 11, 12 8, 9 4, 5 2, 3 PWD DESCRIPTION 1 DDRT0, DDRC0 1 SDRAM12 SDRAM10 1 SDRAM11 SDRAM8 1 SDRAM9 SDRAM6 1 SDRAM7 SDRAM4 1 SDRAM5 SDRAM2 1 SDRAM3 SDRAM1 1 SDRAM0
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ICS93725
Absolute Maximum Ratings
Supply Voltage (VDD & VDD2.5) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85C; (unless otherwise stated) PARAMETER Operating Supply Current Output High Current Output Low Current High-level output voltage Low-level output voltage
1
SYMBOL IDD3.3 IOH IOL VOH VOL
CONDITIONS 100MHz, RL=0, CL = 0pF 133MHz, RL=0, CL = 0pF 200MHz, RL=0, CL = 0pF VDD=3.3V, VOUT=1V VDD=3.3V, VOUT=1.2V VDD=3.3V IOH = -12 mA VDD=3.3V IOH = 12 mA VI = GND or VDD
MIN
TYP 130 173 247 -40 34 2 0.4 2
MAX
UNITS mA mA
-18
26 1.7
mA mA V
0.6
V pF
1 CIN Input Capacitance Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs VDD=3.3V, TA=0 - 85C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN VDD3.3 3 Power Supply Voltage VIH SEL_DDR, PD# input 2 Input High Voltage VIL SEL_DDR, PD# input Input Low Voltae VIN Input Voltage Level 0
1
TYP 3.3
MAX 3.6 0.8 3.6
3.3
UNITS V V V V
Guaranteed by design, not 100% tested in production.
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ICS93725
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 100MHz, RL=0, CL = 0pF IDD2.5 Operating Supply Current 133MHz, RL=0, CL = 0pF 200MHz, RL=0, CL = 0pF VDD=2.5V, VOUT=1V IOH Output High Current VDD=2.5V, VOUT=1.2V IOL Output Low Current VDD=2.5V VOH High-level output voltage IOH = -12 mA VDD=2.5V VOL Low-level output voltage IOH = 12 mA VDD = 2.5V Output differential-pair VOC 100/133/166/ 200 Mhz Crossing voltage 1 CIN VI = GND or VDD Input Capacitance
1
MIN
26 1.7
TYP 141 188 271 -43 38 2 0.4
MAX
-18
UNITS mA mA mA mA mA V
0.6 1.45
V V pF
1.05 2
1.25
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=1 DDR Outputs VDD=2.5V, TA=0 - 85C; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VDD2.5 Power Supply Voltage VIH SEL_DDR, PD# input Input High Voltage VIL SEL_DDR, PD# input Input Low Voltage VIN Input Voltage Level
1
MIN 2.3 2 0
TYP 2.5
MAX 2.7 0.8 2.7
2.5
UNITS V V V V
Guaranteed by design, not 100% tested in production.
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ICS93725
Switching Characteristics
PARAMETER Operating Frequency Input Clock Duty Cycle DDR Static Phase Error SDRAM Static Phase Error DDR output to output Skew SDRAM output to output Skew DDR Duty Cycle SDRAM Duty Cycle DDR Rise Time DDR Fall Time SDRAM Rise Time SDRAM Fall Time DDR Cycle to Cycle Jitter SDRAM Cycle to Cycle Jitter
1 2
SYMBOL din tped tpes Tskewd Tskews DC DC
2
CONDITIONS
MIN 66 40 -100 -100
TYP
-50 -20 60 200
MAX 200 60 100 100 100 300 52 53 52 56 0.95 1.15 1.7 1.8 38 57
UNITS MHz % ps ps ps ps % % % % ns ns ns ns ps ps
2
trd tfd trs tfs t(C-C)D t(C-C)S
Not including FBOUT to outputs Not including FBOUT to outputs 66MHz to 100MHz 101MHz to 200MHz 66MHz to 100MHz 101MHz to 200MHz Measured between 20% and 80% output, CL=16pF VOL = 0.4V, VOH = 2.4V, CL=30pF SEL_DDR=1,VDD=2.5V , CL=16pF SEL_DDR=0,VDD=3.3V , CL=30pF
48 48 48 48 0.55 0.63 0.5 0.5 23 36
0.68 0.91 1.4 1.65
Guaranteed by design, not 100% tested in production. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=t2/t1, where the cycle (t1) decreases as the frequency goes up.
Switching Waveforms
Duty Cycle Timing
t2
1.5V 1.5V
t1
1.5V
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
t7
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ICS93725
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK
ACK Byte Count Byte 0
ACK
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Byte 6
ACK
Byte 6
ACK
Byte 7
ACK
Byte 7
Stop Bit
ACK
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93725
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
N 48
-C10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
e
b
SEATING PLANE .10 (.004) C
300 mil SSOP Package
Ordering Information
ICS93725yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0606A--08/01/03
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